Reducing the size of electronic devices while increasing performance and speed is a continuing objective in the electronics industry. Electronic system manufacturers continue to demand components with higher performance and reliability along with reduced physical sizes and manufacturing costs. To accomplish this, increased miniaturization of integrated circuit (“IC”) packages is becoming increasingly essential. In response, modern requirements for semiconductor packaging are increasingly oriented toward smaller and thinner packages having ever higher numbers of input/output (“I/O”) terminals.
IC packages for complex electronic systems typically incorporate one or more interconnected IC chips or dies, which are usually made from a semiconductor material such as silicon (“Si”) or gallium arsenide (“GaAs”). A variety of semiconductor devices may be formed in various layers on IC chips using photolithographic techniques. After manufacture, the IC chips are typically incorporated into packages that are then mounted on printed circuit boards.
IC chip packages typically have numerous external pins that are mechanically attached to conductor patterns on the printed circuit boards by soldering or other known techniques. Typically, the packages in which these IC chips are mounted include a substrate or other chip-mounting device. One example of such a substrate is a leadframe. High-performance leadframes may encompass multi-layer structures including power, ground, and signal layers on separate planes.
IC chips may be attached to a leadframe by use of an adhesive, or by other commonly employed techniques such as soldering. A number of power, ground, and/or signal leads is then attached to power, ground, and/or signal sites on the IC chip.
Once an IC chip is attached mechanically and electrically to the leadframe, the leadframe may be enclosed or encapsulated in a protective enclosure such as plastic, or a multi-part housing made of plastic, ceramic, or metal. The enclosure helps to protect the leadframe and the attached IC chip from physical, electrical, moisture, and/or chemical damage.
The leadframe and attached chip may then be mounted, for example, on a circuit board or circuit card, typically with other leadframes or devices, for incorporation into any of a wide variety of end products.
Typical known leadframes that include a number of layers on different planes are complex and expensive to produce. Multiple planes have nevertheless been incorporated into the design of many leadframes in order to accommodate the high density of leads needed for the highly complex IC chips typically used today.
Another solution for providing a high density of leads is a multiple-row leadframe in which independent inner and outer rows of leads are provided in a common plane. One such configuration, for example, provides a dual-row pattern in which an inner row of leads is surrounded by an outer row, either in staggered or in-line configurations.
“Leadless” packages are becoming increasingly important as component and circuit designs become ever smaller and smaller. In such leadless packages, the internal leads of the leadframe terminate as contacts on the exterior surface of the package rather than as external wires or leads extending outwardly from the package surface. In this manner, some of the contacts, for example those coming from the internal inner row leads, can be located on the package surface inwardly and away from the package edge. This positions the inner row contacts away from other contacts that are on the package edge (such as, for example, contacts from the outer row leads). More contacts can thus be accommodated without requiring a larger and longer package edge, since not all the contacts are crowded together just at and along the package edge.
One such leadles package is a equal flat no lead (“QFN”) package. QFN packages with higher numbers of input and output (“I/O”) connections in the same (or smaller) body sizes are increasingly important for successful and competitive end-product designs. One key factor that is helping to achieve the higher number of I/Os in such compact end-product designs is a dual-row internal lead arrangement incorporated into leadless QFN packages. These designs have inner row leads and outer row leads (either staggered or in-line), usually in the same plane.
Unfortunately, as the leadframe elements become smaller and smaller in such designs, they also become thinner and less robust, which makes them increasingly susceptible to displacement, such as bending or tilting, while they are being encapsulated. The supports for the inner leads, in particular, are weaker than those for the outer leads. The inner leads are therefore even more likely to be displaced in this manner by the encapsulant as the encapsulant flows over and through the leadframe during the molding process. This displacement moves the leads from their proper positions and allows the encapsulant to seep under the leads, causing mold flash underneath the pad terminals. This in turn causes the leads to be partially or completely covered with the encapsulant at the package surface, which results in a defective package.
Thus, a need remains for leadframe designs, configurations, and manufacturing methods that will maintain the leads in their proper positions during the flow of the encapsulant in the package molding process. In view of the ever-decreasing sizes of leadframes, the ever-increasing numbers of leads on such leadframes, and the persistent need to reduce costs and increase efficiencies, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.